Tender Notice for VLSI DSP and ECA Lab in JEHANABAD, BIHAR
Deadline
13 Aug 2025
Location
JEHANABAD, BIHAR
Tender Progress
Science And Technology Department has released a public tender for VLSI DSP and ECA Lab in JEHANABAD, BIHAR. Quantity: 1. Submission Deadline: 13-08-2025 17:00:00. Download documents and apply online.
Tender Key Details
Organization
Science And Technology Department
Department
Science & Technology Department Bihar
Quantity
1
Bid Validity
90 (Days)
Bid Type
Two Packet Bid
Tender Overview
VLSI DSP and ECA Lab
Important Timeline
Start: 28 Jul 2025
End: 13 Aug 2025
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Additional Information
VLSI DSP and ECA Lab
Item Category
VLSI DSP and ECA Lab
Organization Details
Authority
Organization
Science And Technology Department
Department
Science & Technology Department Bihar
Contact
State
BIHAR
Documents & Downloads
GeM-Bidding-8124948.pdf
Main Document
Other Documents
OTHER
Buyer uploaded ATC document
ATC
GEM General Terms and Conditions Document
GEM_GENERAL_TERMS_AND_CONDITIONS
Required Documents from Seller
Experience Criteria,Past Performance,Bidder Turnover,Certificate (Requested in ATC),OEM Authorization Certificate,OEM Annual Turnover,Compliance of BoQ specification and supporting document *In case any bidder is seeking exemption from Experience / Turnover Criteria, the supporting documents to prove his eligibility for exemption must be uploaded for evaluation by the buyer
Additional Info
Evaluation Method
Total value wise evaluation
Inspection Required
No
Arbitration
No
Bid to RA
Yes
