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GEM

Open Tender for FPGA Development and Evaluation Board in IDUKKI, KERALA

Bid Publish Date

27-Jan-2025, 4:10 pm

Bid End Date

11-Feb-2025, 3:00 pm

Progress

Issue27-Jan-2025, 4:10 pm
AwardPending
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Quantity

10

Categories 1

Directorate Of Technical Education invites bids for FPGA Development and Evaluation Board (Q3) in IDUKKI, KERALA. Quantity: 10. Submission Deadline: 11-02-2025 15: 00: 00. Submit your proposal before the deadline.

Additional Tender Data

Commercial Details

Tender Category

Goods

Bid To RA

No

Bid To RA Enabled

No

Item Category

FPGA Development and Evaluation Board (Q3)

Authority Records

HIGHER EDUCATION DEPARTMENTDIRECTORATE OF TECHNICAL EDUCATION

BID & GeM Expert Consultancy

End-to-end support — bid preparation, GeM registration, document filing & compliance by industry experts.

Bid Preparation GeM Registration Document Filing

Free consultation · 24h response

Documents 3

GeM-Bidding-7436113.pdf

Main Document

WORLD BANK TERMS AND CONDITIONS: Special Terms and Conditions as defined by world bank at click here will also be applicable. APPLICABLE ONLY IN CASE OF WORLD BANK FUNDED PROJECTS.

Referenced Document

attached categories, trials are allowed as per approved procurement policy of the buyer nodal Ministries)

Referenced Document

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Closed: 21 November 2025
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Historical Data

Required Documents

1

Experience Criteria

2

Past Performance

3

Bidder Turnover

4

OEM Authorization Certificate

5

OEM Annual Turnover *In case any bidder is seeking exemption from Experience / Turnover Criteria

6

the supporting documents to prove his eligibility for exemption must be uploaded for evaluation by the buyer

Frequently Asked Questions

Key insights about KERALA tender market

What are the eligibility requirements for suppliers participating in GEM/2025/B/5873052?

The eligibility requirements include being a registered entity under applicable laws, possessing 3 years of relevant experience in supplying FPGA technology, maintaining an average annual turnover of 1 Lakh (INR), and presenting an OEM Authorization Certificate. Bidders seeking exemption from these criteria must provide supportive documentation for evaluation.

What technical specifications must the FPGA Development and Evaluation Boards meet?

The technical specifications for the FPGA Development and Evaluation Boards require compatibility with popular development settings and ample interfaces for educational tasks. Bidders must refer to the detailed specifications in the main tender document, ensuring that their submissions meet the quality standards set by the Higher Education Department Kerala.

What are the performance security and Earnest Money Deposit (EMD) requirements?

Bidders are expected to submit an Earnest Money Deposit (EMD) along with their proposal, as outlined in the tender regulations. This money serves as a security measure ensuring the bidder's commitment. Upon contract award, successful bidders may also need to provide a Performance Security to guarantee fulfillment of their obligations.

How should bids be submitted for this tender?

Bids should be submitted electronically via the specified online platform mentioned in the main document. Bidders must ensure all required documents are uploaded in acceptable formats, and proposals must be complete to avoid disqualification during the evaluation process.

Are there any benefits available for Micro and Small Enterprises (MSEs) under this tender?

Yes, the tender includes benefits for Micro, Small, and Medium Enterprises (MSEs), facilitating their participation and competition in public sector procurement. Additionally, startups looking to participate will find provisions that support their growth under this procurement framework, encouraging innovation and local production in line with 'Make in India' policies.

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