Bid Publish Date
25-Sep-2026, 12:12 pm
Bid End Date
16-Oct-2026, 12:00 pm
Location
Progress
Centre For Development Of Advanced Computing (c-dac) announces a tender for formalISA® Verification IP for C-DAC VEGA Processor variants ET1037, AT1051 and AS1061 Verification in THIRUVANANTHAPURAM, KERALA. Quantity: 1. Submission Deadline: 16-10-2026 12: 00: 00. Last date to apply is approaching fast!
Quantity
1
Bid Type
Two Packet Bid
Bid Validity
180 (Days)
Bid Type
Service
Evaluation
Total value wise evaluation
Inspection Required
No
Tech Clarification Time
2 Days
EMD Required
No
MII Purchase Preference
Yes
MII Preference Band
L1+20%
MSE Purchase Preference
Yes
MSE Preference Band
L1+15%
MSE Exemption/Relaxation
Yes
Startup Exemption/Relaxation
Yes
Bid Splitting Applied
No
Arbitration Clause
No
Mediation Clause
No
Tender Category
Goods
Bid To RA
No
Bid To RA Enabled
No
Item Category
formalISA® Verification IP for C-DAC VEGA Processor variants ET1037, AT1051 and AS1061 Verification
Advisory Bank
State Bank of India
ePBG Percentage
3%
ePBG Duration (Months)
14
Max Delivery Days
84
Delivery Locations
1
Delivery Cities
Thiruvananthapuram
Delivery Pincodes
695033
| Consignee | Address | City | State | Pincode | Quantity | Delivery Days | Additional Requirement |
|---|---|---|---|---|---|---|---|
| Dhanya S | 695033,Purchase Department, Centre for Development of Advanced Computing, Vellayambalam | Thiruvananthapuram | Kerala | 695033 | 1 | 84 | - |
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Main Document
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GEM_GENERAL_TERMS_AND_CONDITIONS
Certificate (Requested in ATC) *In case any bidder is seeking exemption from Experience / Turnover Criteria
the supporting documents to prove his eligibility for exemption must be uploaded for evaluation by the buyer