FPGA Development and Evaluation Board
Directorate Of Purchase And Stores
MUMBAI, MAHARASHTRA
Bid Publish Date
19-Dec-2024, 12:12 pm
Bid End Date
02-Jan-2025, 1:00 pm
Value
₹80,000
Location
Progress
Quantity
1
Bid Type
Two Packet Bid
Indian Institutes Of Science Education And Research (iiser) invites bids for FPGA Development and Evaluation Board (Q3) in PUNE, MAHARASHTRA. Quantity: 1. Submission Deadline: 02-01-2025 13: 00: 00. Submit your proposal before the deadline.
Tender Category
Goods
Bid To RA
No
Bid To RA Enabled
No
Item Category
FPGA Development and Evaluation Board (Q3)
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Main Document
TECHNICAL
GEM_CATEGORY_SPECIFICATION
ATC
GEM_GENERAL_TERMS_AND_CONDITIONS
Directorate Of Purchase And Stores
MUMBAI, MAHARASHTRA
Directorate Of Purchase And Stores
MUMBAI, MAHARASHTRA
Centre For Development Of Advanced Computing (c-dac)
THIRUVANANTHAPURAM, KERALA
Indian Space Research Organization
AHMEDABAD, GUJARAT
Society For Applied Microwave Electronic Engineering And Research (sameer)
CHENNAI, TAMIL NADU
Tender Results
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Experience Criteria
Past Performance
Bidder Turnover
Certificate (Requested in ATC)
OEM Authorization Certificate
OEM Annual Turnover
Additional Doc 1 (Requested in ATC)
Compliance of BoQ specification and supporting document *In case any bidder is seeking exemption from Experience / Turnover Criteria
the supporting documents to prove his eligibility for exemption must be uploaded for evaluation by the buyer
Extended Deadline
10-Jan-2025, 1:00 pm
Opening Date
10-Jan-2025, 1:30 pm
Key insights about MAHARASHTRA tender market
The eligibility requirements necessitate that bidders must be registered entities with at least 3 years of experience in similar services, along with meeting an OEM Average Turnover of 1 Lakh (s) for the past three years.
Bidders are required to submit multiple certificates, including an OEM Authorization Certificate, documents confirming the bidder turnover, evidence of past performance, and any other specific certificates requested in the Additional Terms and Conditions (ATC).
To register for the tender, a bidder must complete the necessary profile on the GeM platform, ensuring all required documentation is attached and eligibility criteria are met before submitting their bid.
Bidders should submit their documents in common formats, including PDF, DOC, and XLS. All files must be clearly labeled and adhere to the guidelines specified in the tender documents.
The technical specifications for the FPGA Development and Evaluation Boards can be found in the Bid Document, where details about the processing capabilities, compatibility, and additional features required are outlined.
Bidders must adhere to ISO standards or other relevant quality benchmarks as outlined by the Department of Higher Education in the tender documentation to ensure compliance.
Yes, bidders must comply with all quality specifications and regulations set forth, including necessary documentation to ensure adherence to the specified requirements.
Testing criteria involve verification against the provided BoQ specifications and assurance measures to demonstrate that the boards meet educational benchmarks and performance standards.
In this specific tender, an EMD is not required. However, bidders must ensure all other financial documentation is complete as outlined.
No performance security is required as per the current tender documentation, allowing for more accessible participation.
Details regarding the payment terms will be specified upon award confirmation but typically require compliance with all terms outlined in the tender documents.
Price evaluations are conducted alongside technical evaluations. The Total value wise evaluation will assess the most competitive bids against technical compliance measures.
Bids must be submitted electronically through the GeM portal, ensuring all required documents and compliance forms are correctly attached before closing.
While specific dates are outlined in the tender documentation, bidders should focus on ensuring their submission is complete well before the closing time to avoid last-minute complications.
MSEs are exempt from the experience and turnover criteria under specific conditions; thereby, if they meet the quality and technical specifications, they can participate with fewer restrictions.
Yes, startups enjoy similar exemptions as MSEs, allowing them to bypass certain financial and experience requirements, provided they meet essential quality and technical specifications.
Compliance with 'Make in India' policies promotes local manufacturing and is generally encouraged within government tenders, though specifics can be referenced in the documentation provided.
Prospective bidders should familiarize themselves with local content procurement guidelines as outlined by the buyer's policies; adherence to these standards could influence the selection process favorably.
Directorate Of Purchase And Stores
📍 MUMBAI, MAHARASHTRA
Indian Institute Of Technology (iit)
N/a
📍 CHITTOOR, ANDHRA PRADESH
Indian Space Research Organization
📍 BANGALORE, KARNATAKA
Indian Space Research Organization
📍 BANGALORE, KARNATAKA
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Main Document
TECHNICAL
GEM_CATEGORY_SPECIFICATION
ATC
GEM_GENERAL_TERMS_AND_CONDITIONS