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GEM

Contract Bidding Open For FPGA Development and Evaluation Board

Bid Publish Date

27-Feb-2026, 5:27 pm

Bid End Date

20-Mar-2026, 6:00 pm

EMD

₹42,000

Progress

Issue27-Feb-2026, 5:27 pm
AwardPending
Explore all 4 tabs to view complete tender details

Quantity

30

Bid Type

Two Packet Bid

Public procurement opportunity for Indian Institute Of Technology (iit) FPGA Development and Evaluation Board (Q3). Quantity: 30 issued by. Submission Deadline: 20-03-2026 18: 00: 00. View full details and respond.

Documents 4

GeM-Bidding-9055302.pdf

Main Document

CATALOG-Specification-1

CATALOG Specification

Buyer uploaded ATC document

ATC

GEM General Terms and Conditions Document

GEM_GENERAL_TERMS_AND_CONDITIONS

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Technical Specifications 1 Item

Item #1 Details

View Catalog
Category Specification Requirement
Processor APU Dual A9
Processor Main Memory DDR3, 512MB, 1066 MT/s, soldered
Programmable Logic # of logic cells 85K
Programmable Logic # of DSP SLICE 220
Programmable Logic # of MMCM 4
Additional Parameters Additional Info Manufacturers University Program Authorization Letter
Warranty/Service Warranty 0.25 Or higher

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Required Documents

1

Experience Criteria

2

Past Performance

3

Bidder Turnover

4

Certificate (Requested in ATC)

5

OEM Authorization Certificate

6

OEM Annual Turnover *In case any bidder is seeking exemption from Experience / Turnover Criteria

7

the supporting documents to prove his eligibility for exemption must be uploaded for evaluation by the buyer

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