FPGA Development and Evaluation Board
National Institute Of Electronics And Information Technology - Nielit (formerly Doeacc Society)
Posted:
5 December 2024
Closed:
16 December 2024
GEM
GEM
Office Of Dg (mss) FPGA Development and Evaluation Board Procurement New Delhi 2026 ISO/IS 550 Compliant
Bid Publish Date
24-Feb-2026, 11:58 am
Bid End Date
11-Mar-2026, 12:00 pm
Location
HYDERABAD , TELANGANA
Progress
Issue24-Feb-2026, 11:58 am
AwardPending
Quantity
3
Bid Type
Two Packet Bid
Categories
1
Tender Overview
The procurement is issued by the Office Of Dg (mss) under the Department Of Defence Research & Development for an FPGA Development and Evaluation Board. The scope is to supply FPGA hardware, with product categories including Processor APUs, Main Memory, and Programmable Logic components. The tender includes a 25% quantity adjustment clause during contract execution and requires extensive techno-commercial documentation, including PAN, GST, and EFT mandates. A data sheet upload is mandatory to enable technical verification against offered specifications. A manufacturer-based purchase preference is indicated for eligible bidders with OEM or MII declarations. The project location details are not disclosed in the available data.
Technical Specifications & Requirements
- Product/service: FPGA Development and Evaluation Board; Primary categories include: APU (Processor), Main Memory, and Programmable Logic components.
- Key technical metrics (as per BOQ/terms): # of logic cells, # of DSP SLICE, # of MMCM; additional information field (Additional Info) and warranty terms.
- Documentation requirements: upload Data Sheet with bid, ensure exact parameter match; bidders must provide TI/IS standards where applicable and a GST invoice along with GST portal payment confirmation.
- Scope of supply: Only supply of Goods. Preference clauses favor manufacturers with OEM/MII declarations and required certifications.
- Compliance: ensure product specifications align with the data sheet and offered parameters; mismatch may lead to bid rejection.
Terms, Conditions & Eligibility
- Quantity flexibility: Purchaser may adjust quantity ±25% during contract at contracted rates; delivery timelines extend proportionally with a minimum of 30 days.
- Vendor code and banking: submit PAN, GSTIN, Cancelled Cheque, and ** EFT Mandate** certified by bank.
- Commercial documents: upload stamped tech-commercial documents, warranty terms, ATP/SOW if applicable, and OEM authorization where required.
- Purchase preference: reserved for technically qualified manufacturers; include UDYAM/MSE certificates and OEM/MII declarations where applicable.
- Data integrity: data sheets must match offered specifications; mismatches trigger technical rejection.
Key Specifications
-
Product/service name: FPGA Development and Evaluation Board
-
Categories: Processor APUs, Main Memory, Programmable Logic
-
Key numeric parameters: # of logic cells, # of DSP SLICE, # of MMCM
-
Warranty: required but not quantified in available data
-
Documentation: mandatory Data Sheet upload; data sheet must align with offered parameters
Terms & Conditions
-
EMD/Financials: Not specified in data; ensure GST/PAN and bank details as per ATC
-
Delivery: 25% quantity variation allowed; minimum 30 days extension
-
Purchase preference: Manufacturer status with OEM/MII declarations and relevant certificates
Important Clauses
Payment Terms
Delivery-based payments with GST invoice submission and GST portal payment screenshot; exact terms not specified in data
Delivery Schedule
Delivery period governed by option clause with computed extension based on quantity change; minimum 30 days
Penalties/Liquidated Damages
Penalty details not specified in available data; standard vendor compliance implied
Bidder Eligibility
-
Manufacturers must provide OEM/MII declarations to qualify for purchase preference
-
UDYAM/MSE certificates should be uploaded where applicable
-
Data sheet alignment with offered product specifications is mandatory for technical eligibility
Documents 4
GeM-Bidding-9016298.pdf
Main Document
CATALOG-Specification-1
CATALOG Specification
Buyer uploaded ATC document
ATC
GEM General Terms and Conditions Document
GEM_GENERAL_TERMS_AND_CONDITIONS
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NIELIT Leh FPGA Development and Evaluation Board Procurement Jammu & Kashmir 2025
National Institute Of Electronics And Information Technology - Nielit (formerly Doeacc Society)
LEH, JAMMU & KASHMIR
Posted:
15 December 2025
Closed:
25 December 2025
GEM
Tender Results
Loading results...
Technical Specifications
1 Item
Item #1 Details
View Catalog| Category | Specification | Requirement |
|---|---|---|
| Processor | APU | Dual A9 |
| Processor | Main Memory | DDR3, 512MB, 1066 MT/s, soldered |
| Programmable Logic | # of logic cells | 13K, 256K |
| Programmable Logic | # of DSP SLICE | 900 |
| Programmable Logic | # of MMCM | 16 |
| Additional Parameters | Additional Info | Manufacturers Authorization Letter |
| Warranty/Service | Warranty | 0.0383299110198494 Or higher |
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Required Documents
1
GST certificate
2
PAN card
3
Cancelled cheque
4
EFT Mandate certified by Bank
5
Data Sheet of offered product(s)
6
GST invoice and GST portal payment screenshot
7
Techno-commercial documents (specifications/scope/ATP/vendor qualification criteria)
8
GEM Bid Document / checklist (if applicable)
9
OEM authorization / Manufacturer details / MII declaration (where applicable)
Frequently Asked Questions
How to bid for FPGA development board tender in India 2026?
Bidders must submit GST certificate, PAN, cancelled cheque, and EFT mandate along with Data Sheet of the offered FPGA board. Ensure the data sheet matches technical parameters (logic cells, DSP slices, MMCM) and upload tech-commercial documents stamped with company seal. OEM authorization may be required; purchase preference for manufacturers with MII/UDYAM declarations.
What documents are required for FPGA bid submission in DRDO procurement?
Required documents include GST registration, PAN, bank details with EFT mandate, cancelled cheque, Data Sheet of the offered FPGA board, GST invoice and GST portal payment screenshot, tech-commercial compliance documents, and OEM authorization if applicable. Ensure stamped copies and signatures for technical evaluation.
What are the key technical specifications for the FPGA board tender?
Key specs include Processor APUs, Main Memory, and Programmable Logic, with explicit counts for # of logic cells, # of DSP SLICE, and # of MMCM. A Data Sheet must align with these parameters; warranty terms are stated but exact duration not provided in the data.
When is the HP/DRDO FPGA board delivery deadline under option clause?
Delivery timelines permit a 25% quantity variation at contracted rates, with extension time calculated as (Increase/Original) × Original delivery period, minimum 30 days, and may extend to the original delivery period. The exact base delivery period is not specified in the available data.
What is required for purchase preference in FPGA bids for manufacturers?
Manufacturers must upload OEM/MII declarations and relevant documents such as UDYAM or MSE certificates to qualify for purchase preference. Preference applies to technically qualified bidders who are the actual manufacturers of the offered FPGA products.
How to ensure data sheet alignment for FPGA bid submission?
Upload the Data Sheet with the bid and verify that all technical parameters match the offered product exactly. Any unexplained mismatch can lead to rejection during technical evaluation, so cross-check logic cells, DSP slices, and MMCM counts against the data sheet.
What payment terms exist for DRDO FPGA procurement bids?
Payments require GST-compliant invoicing; bidders must upload GST invoice and GST portal payment confirmation. The exact payment timeline is not specified in the provided data; bidders should anticipate standard terms linked to delivery and acceptance.
What are the eligibility criteria for DRDO FPGA tender participation?
Eligibility centers on being a manufacturer with OEM authorization or MII declaration for the offered FPGA board, submission of stamped techno-commercial documents, and compliance with data sheet parameters. UDYAM/MSE certificates may fulfill part of the conditions for purchase preference.
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Documents 4
GeM-Bidding-9016298.pdf
Main Document
CATALOG-Specification-1
CATALOG Specification
Buyer uploaded ATC document
ATC
GEM General Terms and Conditions Document
GEM_GENERAL_TERMS_AND_CONDITIONS