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Tender Notice for FPGA Development and Evaluation Board in HARIDWAR, UTTARAKHAND

Bid Publish Date

19-Feb-2026, 3:29 pm

Bid End Date

02-Mar-2026, 4:00 pm

Progress

Issue19-Feb-2026, 3:29 pm
AwardPending
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Quantity

10

Bid Type

Single Packet Bid

Indian Institute Of Technology (iit) has released a public tender for FPGA Development and Evaluation Board (Q3) in HARIDWAR, UTTARAKHAND. Quantity: 10. Submission Deadline: 02-03-2026 16: 00: 00. Download documents and apply online.

Documents 3

GeM-Bidding-9012685.pdf

Main Document

CATALOG-Specification-1

CATALOG Specification

GEM General Terms and Conditions Document

GEM_GENERAL_TERMS_AND_CONDITIONS

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NIELIT Leh FPGA Development and Evaluation Board Procurement Jammu & Kashmir 2025

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LEH, JAMMU & KASHMIR

Posted: 15 December 2025
Closed: 25 December 2025
GEM

Technical Specifications 1 Item

Item #1 Details

View Catalog
Category Specification Requirement
Processor APU Dual A9
Processor Main Memory DDR3, 512MB, 1066 MT/s, soldered
Programmable Logic # of logic cells 85K
Programmable Logic # of DSP SLICE 220
Programmable Logic # of MMCM 4
Additional Parameters Additional Info Manufacturers Authorization Letter, Manufacturers University Program Authorization Letter
Warranty/Service Warranty 0.25 Or higher

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Required Documents

1

Experience Criteria

2

Past Performance

3

Bidder Turnover

4

Certificate (Requested in ATC)

5

OEM Authorization Certificate

6

OEM Annual Turnover *In case any bidder is seeking exemption from Experience / Turnover Criteria

7

the supporting documents to prove his eligibility for exemption must be uploaded for evaluation by the buyer

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