FPGA Development and Evaluation Board
National Institute Of Electronics And Information Technology - Nielit (formerly Doeacc Society)
Bid Publish Date
19-Feb-2026, 3:29 pm
Bid End Date
02-Mar-2026, 4:00 pm
Location
Progress
Quantity
10
Bid Type
Single Packet Bid
Indian Institute Of Technology (iit) has released a public tender for FPGA Development and Evaluation Board (Q3) in HARIDWAR, UTTARAKHAND. Quantity: 10. Submission Deadline: 02-03-2026 16: 00: 00. Download documents and apply online.
Main Document
CATALOG Specification
GEM_GENERAL_TERMS_AND_CONDITIONS
National Institute Of Electronics And Information Technology - Nielit (formerly Doeacc Society)
Indian Institute Of Technology (iit)
Indian Institute Of Technology (iit)
Indian Institute Of Technology (iit)
National Institute Of Electronics And Information Technology - Nielit (formerly Doeacc Society)
LEH, JAMMU & KASHMIR
Tender Results
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| Category | Specification | Requirement |
|---|---|---|
| Processor | APU | Dual A9 |
| Processor | Main Memory | DDR3, 512MB, 1066 MT/s, soldered |
| Programmable Logic | # of logic cells | 85K |
| Programmable Logic | # of DSP SLICE | 220 |
| Programmable Logic | # of MMCM | 4 |
| Additional Parameters | Additional Info | Manufacturers Authorization Letter, Manufacturers University Program Authorization Letter |
| Warranty/Service | Warranty | 0.25 Or higher |
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Experience Criteria
Past Performance
Bidder Turnover
Certificate (Requested in ATC)
OEM Authorization Certificate
OEM Annual Turnover *In case any bidder is seeking exemption from Experience / Turnover Criteria
the supporting documents to prove his eligibility for exemption must be uploaded for evaluation by the buyer
Office Of Dg ( Med & Cos)
📍 BANGALORE, KARNATAKA
Indian Space Research Organization
📍 THIRUVANANTHAPURAM, KERALA
Commissionerate Of Technical Education
📍 BHARUCH, GUJARAT
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Main Document
CATALOG Specification
GEM_GENERAL_TERMS_AND_CONDITIONS