GEM

Government Tender Published for FPGA Development and Evaluation Board in BANGALORE, KARNATAKA

Bid Publish Date

10-Nov-2025, 11:40 am

Bid End Date

01-Dec-2025, 12:00 pm

Bid Opening Date

01-Dec-2025, 12:30 pm

Progress

Issue10-Nov-2025, 11:40 am
AwardPending
Explore all 4 tabs to view complete tender details

Quantity

4

Bid Type

Two Packet Bid

Categories 1

Indian Space Research Organization has released a public tender for FPGA Development and Evaluation Board (Q3) in BANGALORE, KARNATAKA. Quantity: 4. Submission Deadline: 01-12-2025 12: 00: 00. Download documents and apply online.

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Technical Specifications 1 Item

Item #1 Details

View Catalog
Category Specification Requirement
Processor APU Dual A9, Quad A53, NA, RISC-V RV64GC U54
Processor GPU No
Processor Main Memory DDR4, 4GB, 2133 MT/s, upgradeable
Processor RPU No
Processor Video Codec Yes
Programmable Logic # of logic cells 1176K
Programmable Logic # of DSP SLICE 1920
Programmable Logic # of MMCM 4
Peripheral Connectivity USB 2.0 Host 1 x OTG
Peripheral Connectivity MiniPCIe / mSATA dual slot No
Peripheral Connectivity USB Type-C 3.1 Gen1 Dual-Role Device No
Network Connectivity On-board Wi-Fi No
Network Connectivity SFP+ 10G Ethernet No
Network Connectivity WLAN / WWAN / LoRa No
Network Connectivity Ethernet 1G w/ IEEE 1588 Yes
Storage Flash NA
Storage SSD No
Storage SD 25 MB/s
Multimedia HDMI Source Yes
Multimedia Audio Codec No
Multimedia HDMI Sink No
Multimedia DisplayPort No
Multimedia Pcam No
Multimedia Camera NA
Expansion High-speed - FMC Gigabit Yes
Expansion Mid-speed - SYZYGY No
Expansion Low speed - Pmod NA
Expansion Mid-speed - FMC No
Expansion FMC HPC FMC
Additional Parameters Additional Info Manufacturers Authorization Letter
Additional Parameters Power External
Warranty/Service Warranty 0.25 Or higher

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