FPGA Development and Evaluation Board
Indian Institute Of Technology (iit)
Bid Publish Date
27-Nov-2025, 1:59 pm
Bid End Date
10-Dec-2025, 2:00 pm
Progress
Quantity
1
Bid Type
Two Packet Bid
The Directorate Of Purchase And Stores, under the Department Of Atomic Energy, invites bids for the sole supply of a specific FPGA development and evaluation board model: EK-U1-KCU105-G from KiNetworking/KiNova (as referenced by the ATC). Scope emphasizes supply of Goods only, with no BOQ items. The procurement targets the Kolkata region, with an emphasis on a hardware-software platform capable of high-end FPGA development, clocking in at a clearly defined hardware model that ensures date/port compatibility via LIN input/output match. The tender requires OEM-grade warranty and post-sale service readiness, with a unique model lock to EK-U1-KCU105-G for LOI alignment. This is a specialized procurement targeting the DAE’s FPGA evaluation needs in a controlled environment.
EMD/Performance security via Demand Draft in favor of VECC; PBG allowed
Delivery restricted to specified time windows; GPS-free transport
OEM warranty and nationwide service capability required
Payment security via Demand Draft; PBG optional per GeM GTC; DD copy to be uploaded with hard copy within 15 days
Material delivery within contractually stated period; hindrance register to be maintained for extension requests
Hindrance and delay reporting may influence delivery date refixation; penalties as per contract terms
Proven experience delivering FPGA development boards to government or research institutions
OEM authorized supplier for EK-U1-KCU105-G or equivalent model
Willingness to comply with VECC Kolkata delivery and installation terms
Indian Institute Of Technology (iit)
Centre For Development Of Advanced Computing (c-dac)
THIRUVANANTHAPURAM, KERALA
Indian Institute Of Technology (iit)
Indian Institute Of Technology (iit)
National Institute Of Electronics And Information Technology - Nielit (formerly Doeacc Society)
Tender Results
Loading results...
| Category | Specification | Requirement |
|---|---|---|
| Processor | APU | Quad A53, NA |
| Processor | Main Memory | DDR4, 4GB, 2133 MT/s, upgradeable |
| Programmable Logic | # of logic cells | 530K |
| Programmable Logic | # of DSP SLICE | 1920 |
| Programmable Logic | # of MMCM | 8 |
| Network Connectivity | SFP+ 10G Ethernet | Yes |
| Network Connectivity | Ethernet 1G w/ IEEE 1588 | Yes |
| Storage | Flash | 128 Mib |
| Storage | SSD | Yes |
| Storage | SD | 25 MB/s |
| Multimedia | HDMI Source | Yes |
| Expansion | FMC | LPC FMC and HPC FMC |
| Additional Parameters | Additional Info | Manufacturers Authorization Letter, Manufacturers University Program Authorization Letter |
| Additional Parameters | Power | External |
| Warranty/Service | Warranty | 0.25 Or higher |
Discover companies most likely to bid on this tender
GST registration certificate
PAN card
OEM authorization for EK-U1-KCU105-G
Technical bid/compliance certificates
Past performance certificates for FPGA boards
Delivery/commercial terms including DD for EMD or PBG
Warranty certificates from OEM
Service center details and installation plan
Hindrance register format (Annexure-X)
Bidders must meet eligibility criteria including OEM authorization for EK-U1-KCU105-G, GST/PAN documentation, and prior experience supplying FPGA boards to government entities. Submit technical compliance, EMD/DD, and installation plans; ensure delivery within the contract period and provide OEM warranty certificates at delivery.
Required documents include GST registration, PAN, OEM authorization for EK-U1-KCU105-G, technical bid/compliance certificates, service center details, installation plan, DD/PBG for security, and OEM warranty certificates; delivery terms and hindrance register formats must be included.
Board must support EK-U1-KCU105-G model with SFP+ 10G Ethernet, Ethernet 1G with IEEE 1588, HDMI Source, FMC expansion, and SSD/Flash/SD storage; include required number of logic cells, DSP SLICE, and MMCM as per model; memory and APU requirements align with high-end FPGA platforms.
Payment security is via Demand Draft in favor of VECC; PBG is allowed; scanned DD can be uploaded after award with hard copy delivered within 15 days; GeM terms apply; GST not applicable for inland transits.
Delivery must occur within the contractually specified period after award; hindrance registers may be used to request date refixation; ensure the material is delivered within the delivery window without GPS-enabled transport.
OEM warranty certificates must accompany delivery; service network across India for installation, commissioning, training, and maintenance; provide details of service centers near consignee locations in the bid.
Yes. The bid references DPS/CRPU/VECC/31221; only EK-U1-KCU105-G model acceptable; GPS-free transport; specific delivery hours; no GST credit; hindrance reporting and record maintenance are mandatory for extension consideration.
Office Of Dg (mss)
📍 HYDERABAD, TELANGANA
Indian Institute Of Technology (iit)
📍 CHENNAI, TAMIL NADU
National Institute Of Technology (nit)
📍 TIRUCHIRAPPALLI, TAMIL NADU
Directorate Of Purchase And Stores
📍 JAIPUR, RAJASTHAN
Oil And Natural Gas Corporation Limited
📍 MUMBAI, MAHARASHTRA
Access all tender documents at no cost
Main Document
OTHER
OTHER
CATALOG Specification
ATC
GEM_GENERAL_TERMS_AND_CONDITIONS
Main Document
OTHER
OTHER
CATALOG Specification
ATC
GEM_GENERAL_TERMS_AND_CONDITIONS