FPGA Development and Evaluation Board
Directorate Of Purchase And Stores
MUMBAI, MAHARASHTRA
Bid Publish Date
09-Jun-2026, 10:15 am
Bid End Date
19-Jun-2026, 11:00 am
Location
Progress
Quantity
4
Bid Type
Two Packet Bid
The Government E-Marketplace (GEM) seeks an FPGA development and evaluation board tender for India, featuring programmable logic capabilities including APU integration, main memory support, and DSP SLICE with MMCM facilities. The procurement scope references a board-level product with multiple programmable logic parameters and a warranty clause. While the BoQ shows zero items, the buyer’s terms emphasize flexible quantity management and contract-wide delivery timing. The opportunity is distinguished by the option clause allowing a ±25% quantity adjustment during and after award, at contracted rates, with delivery time recalculations based on the original period. Bidders should align with standard governmental FPGA board specifications and delivery practices.
Product/service names: FPGA development and evaluation board
Quantities/values: not specified; option clause permits ±25% quantity adjustment
EMD/estimated value: not provided; typical GEM tender requires EMD
Experience: capability to supply government FPGA boards; prior similar contracts recommended
Quality/compliance: standard FPGA board performance criteria; warranty to be defined
Quantity variation: ±25% at contracted rates
Delivery time: from last date of original delivery order; min 30 days for extensions
Warranty: board warranty and service terms to be defined in contract
Not specified in provided data; to be defined in contract tied to delivery milestones
Delivery period recalculated if option clause exercised; base period from original delivery order date
Not specified; standard GEM terms may include LDs in contract
Demonstrated FPGA board supply experience to government or large-scale buyers
Ability to meet OEM authorization requirements for FPGA development boards
Financial stability evidenced by turnover/financial statements
Tender Category
Goods
Bid To RA
No
Bid To RA Enabled
No
Item Category
FPGA Development and Evaluation Board (Q3)
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Main Document
CATALOG Specification
GEM_GENERAL_TERMS_AND_CONDITIONS
Directorate Of Purchase And Stores
MUMBAI, MAHARASHTRA
Centre For Development Of Advanced Computing (c-dac)
THIRUVANANTHAPURAM, KERALA
Indian Space Research Organization
AHMEDABAD, GUJARAT
Society For Applied Microwave Electronic Engineering And Research (sameer)
CHENNAI, TAMIL NADU
Directorate Of Purchase And Stores
MUMBAI, MAHARASHTRA
Tender Results
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| Category | Specification | Requirement |
|---|---|---|
| Processor | APU | Quad A53, NA |
| Processor | Main Memory | DDR3, 512MB, 1066 MT/s, soldered |
| Programmable Logic | # of logic cells | 13K, 256K |
| Programmable Logic | # of DSP SLICE | 90 |
| Programmable Logic | # of MMCM | 4 |
| Additional Parameters | Additional Info | Manufacturers Authorization Letter |
| Warranty/Service | Warranty | 0.0 Or higher |
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GST registration certificate
Permanent Account Number (PAN) card
Experience certificates of related FPGA board supply
Financial statements or turnover proof
EMD/Security deposit documentation (as per GEM terms)
Technical bid documents demonstrating FPGA board compatibility and OEM authorizations
OEM authorization letters (if bidding on behalf of manufacturer)
Bidders must submit GST, PAN, financial statements, experience certificates, and technical bid documents with OEM authorizations. Ensure FPGA board model supports APU integration, required main memory, and MMCM/DSP specs. Adhere to the 25% quantity option policy and provide a warranty proposal as per contract.
Required documents include GST certificate, PAN, company registration, EMD submission, financial statements, prior experience certificates for FPGA boards, OEM authorization letters, and detailed technical compliance sheets showing board capabilities: logic cells, DSP SLICE, MMCM, and memory support.
Delivery period starts from the last date of the original delivery order. If quantity is increased, additional time = (Increased quantity / Original quantity) × Original delivery period, with a minimum of 30 days. Extensions may raise total delivery time up to the original period.
No specific standards are listed in the provided text. Bidders should align with common government FPGA board criteria and obtain OEM approvals. Include ISI/ISO aligned quality practices if applicable and provide documentation to verify board compliance.
EMD amount is not specified in the tender data provided. Bidders should prepare the standard EMD as per GEM guidelines and ensure payment method aligns with online or DD arrangements, as applicable to the bidding process.
Confirm vendor status with GEM; provide verifiable FPGA supply experience, OEM authorizations, and financial viability. Ensure ability to meet quantity variation up to 25% and demonstrate capability to deliver under government procurement terms within the contract framework.
Warranty scope is not explicitly defined in the provided data. Propose a comprehensive board warranty covering manufacturing defects and support for a defined period in the technical bid, with service terms and replacement policies clarified in the contract.
The option clause allows a ±25% quantity variation at contracted rates. Delivery time for added quantity is recalculated using the original duration rule and subject to a minimum 30 days extension, ensuring feasible timelines for larger orders.
Indian Space Research Organization
📍 AHMEDABAD, GUJARAT
Office Of Dg ( Ns & M)
📍 ERNAKULAM, KERALA
Indian Space Research Organization
📍 THIRUVANANTHAPURAM, KERALA
Bharat Electronics Limited (bel)
📍 BANGALORE, KARNATAKA
Indian Space Research Organization
📍 AHMEDABAD, GUJARAT
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Main Document
CATALOG Specification
GEM_GENERAL_TERMS_AND_CONDITIONS