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Tender Notice for FPGA Development and Evaluation Board in AHMEDABAD, GUJARAT

Bid Publish Date

03-Nov-2025, 12:50 pm

Bid End Date

01-Dec-2025, 1:00 pm

Latest Corrigendum Available

Progress

Issue03-Nov-2025, 12:50 pm
Corrigendum24-Nov-2025
AwardPending
Explore all 4 tabs to view complete tender details

Quantity

5

Bid Type

Two Packet Bid

Categories 1

Commissionerate Of Technical Education has released a public tender for FPGA Development and Evaluation Board (Q3) in AHMEDABAD, GUJARAT. Quantity: 5. Submission Deadline: 01-12-2025 13: 00: 00. Download documents and apply online.

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Technical Specifications 1 Item

Item #1 Details

View Catalog
Category Specification Requirement
Processor APU Dual A9, Quad A53, NA
Processor Main Memory DDR4, 4GB, 2133 MT/s, upgradeable, DDR3, 512MB, 1066 MT/s, soldered
Programmable Logic # of logic cells 102K
Programmable Logic # of DSP SLICE 90, 1920, 2520
Programmable Logic # of MMCM 4
Additional Parameters Additional Info Manufacturers Authorization Letter, Manufacturers University Program Authorization Letter
Warranty/Service Warranty 1.0 Or higher

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Required Documents

1

Experience Criteria

2

Past Performance

3

Bidder Turnover

4

Certificate (Requested in ATC)

5

OEM Authorization Certificate

6

OEM Annual Turnover

7

Additional Doc 1 (Requested in ATC) *In case any bidder is seeking exemption from Experience / Turnover Criteria

8

the supporting documents to prove his eligibility for exemption must be uploaded for evaluation by the buyer

Corrigendum Updates

1 Update
#1

Update

24-Nov-2025

Extended Deadline

01-Dec-2025, 1:00 pm

Opening Date

01-Dec-2025, 1:30 pm

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